Ayar Labs, a startup developing optical interconnects for data centers and supercomputers, has raised $35 million in its second round of funding. The company said that it would use the proceeds to roll out its silicon photonics technology, which paves the way for processors in servers and other areas to communicate with each other using light.
The funding brings the Santa Clara, California-based company's haul to more than $60 million since it was founded in 2015. The funding was led by Downing Ventures and BlueSky Capital, while other investors in the round included Applied Ventures, the investment arm of Applied Materials, as well as Intel Capital, Globalfoundries, Lockheed Martin, and Playground Global.
The startup is trying to transform its optical interconnects into a major component of any system that moves a massive amount of data, including in cloud data centers and colossal supercomputers. Other areas the company is targeting in the future include aerospace and defense systems, 5G networks, and lidar sensors slapped on the sides of autonomous cars.
Today, cloud computing vendors and other titans of the technology industry, such as Google, Microsoft and Amazon, use optical connections in data centers to lash together servers and to connect data centers over long-range cables. But they could use server chips with Ayar's silicon photonics inside to further increase the amount of data these systems can process.
In data centers and supercomputers, data travels constantly while it is processed. Data moves from central processing units (CPUs) to memory to other types of server processors, including graphics processing units (GPUs) that handle deep learning and other workloads. The constant movement means that the time it takes to carry out computing chores depends on the speed of the wires. Today, the data dashes from one chip to another electronically, through copper wires.
But as the performance of processors in servers has soared over the last decade, the electronic interconnects moving data from the memory to the central processor and other chips in servers have struggled to keep pace. The bandwidth of the copper wires has become a major bottleneck to improving performance, power, area and cost in data centers and supercomputers. But solving it could also open the door to new system architectures, which are constrained by copper wires.
Ayar said that its interconnect chips promise to speed up data transfers by moving data from memory to the processor and other components in the server using photons of light, which are faster and more energy-efficient than electrons. The startup said the chips bring improvements of up to 1000 times in throughput compared to traditional copper wires, increasing the system-level performance. Sending data over fiber optics consume up to 10 times less power, it says.
Ayar's technology is based on a decade of research at MIT, UC Berkeley, and the University of Colorado at Boulder, with funding from DARPA, the Department of Defense's research division.
The company's flagship chip, TeraPHY, integrates all the optical and electronic technology on a single, compact silicon die. Available as a chiplet, the slab of silicon can be incorporated on the same package as a central processing unit or server networking chip to give it high-speed data transmission capabilities. The chip communicates with the CPU and other ICs in the package over a standard interface. That way, the chips act as though they are sharing the same die.
The networking chip is based on a novel architecture with eight ports or "light channels" capable of transferring up to tens of trillions of bits of data per second directly out of the processors on the package, translating the light into electronic signals that other server gear can understand. Each port has around the same bandwidth as eight PCIe Gen 5 connections, the startup said.
There are lots of potential advantages to its in-package silicon photonics. The IC could be used to replace more of the copper cables that cloud and other technology giants use to wire vast warehouses of servers, saving money. By replacing bulky networking gear, it could also save space and cut power in servers. The bandwidth boost Ayar is promising could also open the door to more densely packed server clusters that can be cooled more efficiently than today.
The chip contains a die-to-die interface based on the open-source advanced interconnect bus, or AIB, to connect to central processors or other chips from partners slapped on the same package.
The Silicon Valley startup is also winning over major players in the semiconductor industry with its in-package silicon photonics. Intel has partnered with it to integrate optical interconnects on CPUs and other server processors, as part of DARPA's PIPES program. Earlier in the year, Intel said that it had successfully co-packaged TeraPHY with one of its programmable FPGAs using its EMIB silicon-bridge packaging and AIB interface, giving it data transfer rates of up to 2 Tbps.
One way it stands out from rivals is in manufacturing the chip on industry-standard production lines, speeding up its time-to-market. The chip is based on a 45-nm node from Globalfoundries. Early in the year, it started rolling out sample products to chip suppliers, server manufacturers, telecom equipment vendors, and others to cement relationships with early potential customers.
CEO Charles Wuischpard said that it would use the funding to accelerate the development of its in-package optical interconnect devices as well as expand the company's international footprint.
What you’ll learn
- What’s new with NXP’s S32K3 series.
- How lockstep makes a difference with the S32K3.
NXP Semiconductors has used the Cortex-M7 core for a range of automotive microcontroller units (MCUs) starting with the S32K1 series. The new S32K3 series raises all the bars with more memory and performance as well as including features like lockstep mode (Fig. 1). Asymmetric Cortex systems-on-chip (SoCs) are common, but they’re typically a Cortex-M0+ and a higher-end Cortex-M or combined with a Cortex-A application processor. There are single-core S32K3s, but dual- and triple-core versions exist as well, running up to 240 MHz.
1. The S32K3 family scales from a single-core Cortex-M7 through a triple- or dual-core lockstep system.
The S32K family targets automotive applications. They have up to 8 MB of flash and up to 256 kB SRAM memory with ECC support. The flash is setup as two blocks that allow an A/B firmware swap with automatic address translation. Firmware-over-the-air (FOTA) updates load into one block while the system runs from the other block. The switch occurs on reset with the ability to fallback to the original block if there are problems.
The chips are designed for safety-critical applications that meet ISO 26262 ASIL B/D requirements. The family has a fault collection and control unit with an HSE-B security engine that supports AES-128/192/256, RSA, and ECC. This also provides secure boot with key storage and side-channel attack protection. It’s intended to support ISO 21434 automotive security.
The systems have QSPI and serial ports as well as I3C, I2C, and up to eight CAN FD ports. The 10/100-Mb/s Ethernet supports time sensitive networking (TSN) and audio video bridging (AVB). Up to three 24-channel, 12-bit ADCs are available. The 16-bit eMIOS (enhanced modular input/output system) timer with logic control unit can handle motor-control chores.
The S32K3 family comes in BGA and MaxQFP packages (Fig. 2). The MaxQFP is 55% smaller than a conventional QFP while retaining the same number of pins. The architecture uses conventional QFP pins on the outside and a wraparound pin on the edge of the chip. The latter’s solder pad is partially under the chip. There are 10- × 10-mm, 100-pin chips as well as 16- × 16-mm, 172-pin versions of MaxQFP, allowing for pin-compatible replacements using most of the available S32K3 devices. High-pin-count devices are also available in MAPBGA-289 packages.
2. The MaxQFP package (left) reduces the chip footprint by more than 50% (top right). Half of the pins have a conventional QFP layout, while the other half curve under the chip (bottom right).
The hardware is impressive, but software costs often dominate many automotive designs. To this end, NXP provides free ISO 26262-compliant real-time software drivers for AUTOSAR and non-AUTOSAR. They used to provide the latter. Given that most of these chips will need to meet ASIL A/B requirements, the free AUTOSAR drivers can save a significant chunk of change.
The drivers are all part of NXP’s software package that also includes the Safety Framework Software and Core Self-Test library. The framework integrates over half a dozen modules supporting everything from lockstep operation to security, obviously taking advantage of the underlying hardware.
November 20, 2020 at 06:35AM
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Startup Raises $35 Million to Roll Out Optical Interconnects for Chips - Electronic Design
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